Conventionally, testing of integrated circuits involves placing the microchip under test on a device under test (“DUT”) card connected to a tester. The tester is used to test the integrated circuit for functionality. In instances where the tester is sufficiently fast, the integrated circuit may be tested at a maximum frequency of operation.
Integrated circuits which are more or less standard products are often speed binned. Examples of such standard products include memories, processors and programmable logic devices, among others. One form of programmable logic device which is a standard product is a Field Programmable Gate Array (“FPGA”).
Speed binning an integrated circuit involves testing to determine a frequency, such as the maximum frequency of operation of the integrated circuit, for which it continues to function correctly. Accordingly, some integrated circuits will operate at faster speeds than other same or similarly manufactured integrated circuits whether from same or different production lots. Conventionally, speed binning is used to identify parts that can operate at frequencies in excess of a baseline frequency for sale at a premium price.
The limitation of tester speed is exacerbated by integrated circuits having an embedded processor with frequency of operation significantly faster than a host integrated circuit in which the core is embedded. Another limitation of testers is being able to control, from externally accessible pins of the host integrated circuit, internal pins of the embedded processor, especially when such internal pins significantly out number the externally accessible pins.
Accordingly, it would be desirable and useful to provide means for testing a critical path of an embedded processor in an integrated circuit device with limited, if any, circuitry overhead being added.